行并行可重构单元阵列流水映射性能评估

Pipeline Mapping Performance Evaluation for Row Parallel Reconfigurable Cell Array

摘要:

针对粗粒度单元阵列流水映射问题，设计了三种行流水结构阵列，并分析了其执行步骤，提出了一种基于行流水阵列通用的流水映射算法.该算法综合考虑混合多层迭代启动间距、块间流水通信成本、块配置成本等多个因素，一组测试基准程序实验结果表明了文中算法的合理性，与多目标优化映射算法相比，该算法消耗总时延平均节省了4.0%(可重构单元阵列RCA4×4)和4.3%(可重构单元阵列RCA8×8)；与满射映射相比，该算法消耗总时延平均节省了52.1%(RCA4×4)和56.2%(RCA8×8).

Abstract:

As for the problem of coarsegrained cell array pipeline mapping, this paper designed three row pipeline architecture array, analyzed their execution step, and presented a universal pipeline mapping(PM) algorithm for row pipeline array. This algorithm had comprehensive considered multilevel iteration initiation interval, communication costs between blocks, block reconfigurable costs and etc. The experimental results of a set of benchmark programs show the rationality of the algorithm. Comparing with multiobjective optimization map(MOM), the average execution total cycles of PM saved by 4.0%(reconfigurable cell array, RCA4×4) and 4.3%(reconfigurable cell array, RCA8×8). Comparing with epimorphism map (EPIMap) algorithm, the average execution total cycles of PM saved by 52.1%(RCA4×4) and 56.2%(RCA8×8).