A Kind of Instruction Queue Competition Easing Strategy for Simultaneous Multi threading Architecture

Abstract:

The simultaneous multi threading (SMT) technique boosts instructions per clock (IPC) by adopting thread level parallelism and instruction level parallelism. However, the competition of key resources between threads do weaken such advancement. Instruction queue (IQ) is proved as one key resource and its competition always results into performance degradation. Typical IQ competition easing strategies include Dwarn, 2OP_Block and Static. This paper presets two IQ utilization parameters to estimate the relationships between IQ usage and system performance. Competition easing capability of typical IQ strategies and their combination are compared. A load dependency chain model is built and analysis of thread characteristics based on the model is given. Then a new IQ competition easing strategy combining with thread characteristics is proposed. The experimental results show that such strategy can achieve total IPC improvement by accelerating high IPC threads.