Pipeline Mapping Performance Evaluation for Row Parallel Reconfigurable Cell Array

Abstract:

As for the problem of coarsegrained cell array pipeline mapping, this paper designed three row pipeline architecture array, analyzed their execution step, and presented a universal pipeline mapping(PM) algorithm for row pipeline array. This algorithm had comprehensive considered multilevel iteration initiation interval, communication costs between blocks, block reconfigurable costs and etc. The experimental results of a set of benchmark programs show the rationality of the algorithm. Comparing with multiobjective optimization map(MOM), the average execution total cycles of PM saved by 4.0%(reconfigurable cell array, RCA4×4) and 4.3%(reconfigurable cell array, RCA8×8). Comparing with epimorphism map (EPIMap) algorithm, the average execution total cycles of PM saved by 52.1%(RCA4×4) and 56.2%(RCA8×8).