Pipeline Mapping Performance Evaluation for Row Parallel Reconfigurable Cell Array
CSTR:
Author:
Clc Number:

TP302

  • Article
  • | |
  • Metrics
  • |
  • Reference
  • |
  • Related
  • |
  • Cited by
  • | |
  • Comments
    Abstract:

    As for the problem of coarsegrained cell array pipeline mapping, this paper designed three row pipeline architecture array, analyzed their execution step, and presented a universal pipeline mapping(PM) algorithm for row pipeline array. This algorithm had comprehensive considered multilevel iteration initiation interval, communication costs between blocks, block reconfigurable costs and etc. The experimental results of a set of benchmark programs show the rationality of the algorithm. Comparing with multiobjective optimization map(MOM), the average execution total cycles of PM saved by 4.0%(reconfigurable cell array, RCA4×4) and 4.3%(reconfigurable cell array, RCA8×8). Comparing with epimorphism map (EPIMap) algorithm, the average execution total cycles of PM saved by 52.1%(RCA4×4) and 56.2%(RCA8×8).

    Reference
    Related
    Cited by
Get Citation

CHEN Naijin, FENG Zhiyong, JIANG Jianhui, HE Ruixiang, WANG Zhen. Pipeline Mapping Performance Evaluation for Row Parallel Reconfigurable Cell Array[J].同济大学学报(自然科学版),2017,45(08):1218~1226

Copy
Share
Article Metrics
  • Abstract:1835
  • PDF: 1086
  • HTML: 721
  • Cited by: 0
History
  • Received:October 23,2016
  • Revised:May 16,2017
  • Adopted:April 14,2017
  • Online: September 07,2017
Article QR Code